The present invention relates generally to the field of semiconductor fabrication, more particularly, to a reticle for use in a photolithography process during semiconductor fabrication, and a method for designing such a reticle.
In the manufacture of semiconductor chip devices, photolithographic processes are often used to pattern various layers on a wafer in order to produce circuit features (e.g., transistors or polygates, wing patterns, capacitors, etc.) positioned as specified in a circuit feature layout. In such processes, a layer of resist (also referred to as xe2x80x9cphotoresistxe2x80x9d) is deposited on the layer being patterned, and the resist is then exposed using an exposure tool and a template. These templates are known in the art as reticles or masks. For purposes of the present application, the term reticle includes both reticles and masks. During the exposure process, the reticle is typically placed over the resist, and then a form of radiant energy such as ultraviolet light is directed toward the reticle to selectively expose the resist in a desired pattern. A preferred device for creating such exposure is known as a xe2x80x9cstepper.xe2x80x9d
One type of reticle which has been used is referred to as a binary reticle. A binary reticle includes reticle features, namely transparent features (areas through which exposure passes) and opaque features (areas which block exposure). The design of the reticle features is typically shown in a two-dimensional xe2x80x9creticle layoutxe2x80x9d, although the reticle itself typically includes two or more layers (e.g., a transparent layer and a patterned opaque layer). In use, radiant energy is directed toward the binary reticle, and the rad;ant energy is blocked by the opaque areas but passes through the transparent areas to pattern-wise expose the resist. After pattern-wise exposure, the resist is developed to remove either the exposed portions of the resist (a positive resist) or the unexposed portions of the resist (a negative resist), thereby forming a patterned resist on the layer being patterned. The patterned resist is then used to protect a corresponding pattern of underlying areas on the layer during subsequent fabrication processes, such as deposition, etching or ion implantation processes. Thus, the patterned resist prevents or substantially prevents the effects of the fabrication process(es) from being produced in the layer in areas of the layer which lie beneath portions of the resist which have not been removed. The reticle is designed so as to enable exposing the resist in a pattern which corresponds to the feature or features which are desired to be formed.
There are a number of effects caused by diffraction of exposure which tend to distort the patterns formed in a resist, i.e., which cause the pattern formed in a resist to differ from the pattern formed in the reticle.
Due to limitations imposed by the wavelength of light used to transfer the pattern, resolution degrades at the edges of the patterns of the reticle. Such degradation is caused by diffraction of the exposure such that it is spread outside the transparent areas. Phase shift masks (PSMs) have been used to counteract these diffraction effects and to improve the resolution and depth of images projected onto a target (i.e., the resist covered wafer). There are a variety of PSMs. One kind of PSM includes a phase shifting layer having areas Which allow close to 100% of the exposure to pass through but phase shifted 180 degrees relative to exposure passing through a transparent layer. Attenuated PSMs utilize partially transmissive regions which pass a portion of the exposure, e.g., about three to eight percent, out of phase with exposure through transparent areas. Typically, the shift in phase is 180 degrees, such that the portion of exposure passing through the partially transmissive regions destructively interferes with exposure which is spread outside the transparent areas by diffraction. Phase shift masks can thereby increase image contrast and resolution without reducing wavelength or increasing numerical aperture. These masks can also-improve-depth-of-focus and process latitude for a given feature size. Designs of such reticles typically are represented using one or more two-dimensional reticle layouts including appropriate reticle features, e.g., selected from among transparent features, opaque features, phase shifting features and phase shifting attenuating features.
There has been an ongoing need to increase the density of features contained in semiconductor devices, by making the features smaller and/or reducing the amount of space between features. Advances in feature density have required that reticles include correspondingly smaller and/or more densely packed features. The extent to which features printed by photolithographic methods can be reduced in size is limited by the resolution limit of the exposure device. The resolution limit of an exposure tool is defined as the minimum feature dimension that the exposure tool can repeatedly expose onto the resist, and is a function of the wavelength of exposure emitted by the stepper, the aperture through which exposure is emitted, the depth of focus and other factors. Thus, reticle design is limited in that the gaps between respective features on the reticle (i.e., transparent regions, opaque regions and/or phase shifted regions) must be large enough for the circuit features to be correctly printed.
The critical dimension (CD) of a circuit pattern is defined as the smallest width of a line in the pattern, or the smallest space between lines in the pattern. The CD thus directly affects the size and density of the design. As the density of features in a pattern is increased, the CD of the design approaches the resolution limit of the stepper. As the CD of a circuit layout approaches the resolution limit of the stepper, the diffraction of exposure causes increasingly significant distortions of the pattern being created.
These distortions are known as optical proximity effects. The primary optical proximity effects are that corners of features are rounded, isolated features print differently from identically shaped and sized semi-isolated or densely packed features, smaller features are printed relatively smaller than larger features, and relatively thin line features are shortened. Features which are in close proximity to other features tend to be mores significantly distorted than features which are relatively isolated from other features. Furthermore, optical proximity effect distortion is compounded by subsequent processing step distortions such as resist processing distortions and etching distortions.
As a result, many design techniques have been developed, with the goal being to reduce such distortion. Such techniques, referred to in the art as optical proximity correction (OPC) techniques, involve adding and/or subtracting areas to reticle design patterns such that the pattern formed by exposure through the reticle more closely corresponds to the desired pattern. Typically, OPC is performed on a digital representation of a desired pattern, in which the desired pattern is evaluated with software to identify regions where distortion will occur. Areas which are added to the design, sometimes referred to as xe2x80x9cserifsxe2x80x9d, are typically designed such that their largest dimension is smaller than the resolution of the stepper. As a result, such areas counteract distortion but do not print to the resist.
U.S. Pat. No. 5,821,014 discloses a method comprising using scattering bars between features for correcting for proximity effects. According to the patent, scattering bars are correction features (typically non-resolvable) that are placed next to isolated edges on a mask in order to adjust the edge intensity at the isolated edge to match the edge intensity at a densely packed edge.
U.S. Pat. No. 5,707,765 discloses a method of making a photolithography mask that utilizes serifs to increase the correspondence between an actual circuit design and the final circuit pattern on a semiconductor wafer. The mask uses a plurality of serifs having a size determined by a resolution limit of the optical exposure tool used during the fabrication process. The serifs are positioned on the corner regions of the mask such that a portion of surface area for each of the serifs overlaps the corner regions of the mask. The size of the serifs is about one-third the resolution limit of said optical exposure tool.
However, the addition of serifs according to prior art reticle design techniques limits the extent to which the density of features in a circuit can be increased while still maintaining adequate spacing between the features in reticles used to pattern the resist used to provide such circuit features.
For example, FIG. 1A is a partial view of an example of a desired repetitive circuit feature layout having densely packed circuit features 10, as well as forbidden regions 13 in which features cannot be present. FIG. 1B is a partial view of an example of a reticle layout for use in producing a device having the circuit feature layout shown in FIG. 1A, in which the reticle layout is formed using prior art techniques. As shown in FIG. 1B, the reticle layout having has densely packed printable reticle features 11 and serifs 12. It is necessary that there be at least a minimum amount of space between each of these features, e.g., in order that the reticle can be properly inspected using existing inspection procedures. If such minimum sized gaps are not present, current inspection procedures cannot identify the presence of the gap. As such inspection procedures are developed which can perform inspection despite smaller gaps, the present invention will still be applicable for the same reasons as described above, but with the tolerances of design being adjusted appropriately. FIG. 1C is a partial view of a computer-generated simulation of the pattern of exposure areas 14 which would be exposed if exposure were directed through a reticle having a reticle layout as shown in FIG. 1B. FIG. 1D is a view showing the pattern of FIG. 1C superimposed on the layout of FIG. 1A, demonstrating the variance of the actual pattern which will be produced relative to the desired pattern. This variance, at any given point on the perimeter of a feature 10, is the distance from the point on the perimeter 16 of a feature 10 to the nearest point on the perimeter 15 of an exposure area 14. For example, at point 17 in FIG. 1D, the variance is shown by the length of the line segment identified with reference number 18. Returning to FIG. 1B, as the gaps 19 become smaller, there reaches a point where there is insufficient space between serifs 12 to increase their size to reduce this variance.
Accordingly, in such a situation, the prior art reticle design method has reached the point where the variance between the actual exposure pattern and the desired exposure pattern cannot be substantially improved. Therefore, according to the prior art method the reticle layout of FIG. 1B would be sent to a mask shop or the like, where a reticle would be manufactured which conforms to FIG. 1B. In such a reticle, opaque regions would be formed in all areas other than areas 11 and 12. Thus, for a binary reticle, the completed reticle would include transparent portions in areas 11 and 12, and exposure blocking regions everywhere else. In the case of a phase shift mask, the completed reticle would include transparent portions in areas 11 and 12, and phase shift regions everywhere else.
FIG. 2A is a partial view of a second example of a desired repetitive circuit feature layout having densely packed circuit features 20, as well as forbidden regions 23 in which features cannot be present. FIG. 2B is a partial view of an example of a reticle layout for use in producing a device having the circuit feature layout shown in FIG. 2A, the reticle layout being formed using prior art techniques. The reticle layout has densely packed printable reticle features 21 and serifs 22. FIG. 2C is a partial view of a computer-generated simulation of the pattern which would be exposed if exposure were directed through a reticle having a reticle layout as shown in FIG. 2A. FIG. 2D is a view showing the pattern of FIG. 2C superimposed on the layout of FIG. 2A, demonstrating the variance of the actual pattern which will be produced relative to the desired pattern. Analogously to FIG. 1D, in FIG. 2D. this variance, at any given point on the perimeter of a feature 20, is the distance from the point on the perimeter 26 of a feature 20 to the nearest point on the perimeter 25 of an exposure area 24. For example, at point 27 in FIG. 2D, the variance is shown by the length of the line segment identified with reference number 28. Returning to FIG. 2B, it is seen that there is insufficient space between serifs 22 to increase their size to reduce this variance. In FIG. 2B, as in FIG. 1B, there is insufficient space between serifs 22 to increase their size to reduce this variance. Accordingly, the prior art reticle design method of FIG. 2B has reached the point where the variance between the actual exposure pattern and the desired exposure pattern cannot be substantially improved.
There is an ongoing need for methods of designing reticles which can be used to form features which are packed in patterns which are increasingly more dense, while reducing or eliminating printing errors and decreasing the variance between the actual exposure pattern and the desired exposure pattern.
The present invention provides a method for designing reticles which can be used to produce circuit designs having densely packed circuit features, in which the occurrence of printing errors is reduced or eliminated, and the variance between the actual exposure pattern and the desired exposure pattern is reduced.
According to the present invention, there are provided reticle designs which include sub-resolution connecting structures which connect two or more reticle features. By xe2x80x9csub-resolutionxe2x80x9d is meant a feature on a reticle which, when exposure is directed through the reticle onto a resist, will not print on the resist. For example, a feature on a reticle having at least one dimension which is less than about one third of the wavelength of the exposure used will not print on the resist. The present invention is applicable to all types of reticles, e.g., binary masks and phase shift masks (including attenuated phase shift masks).
In practicing the method of this invention, an initial reticle layout is generated which includes printable reticle features which are sized, shaped and positioned such that if exposure were directed through a reticle having such an initial reticle layout onto a resist, the resist would be exposed in a pattern which roughly approximates the desired circuit feature layout. Each of the printable reticle features corresponds to a separate circuit feature in the desired circuit feature layout. The initial reticle layout may be based on any known, technique, e.g., optical proximity correction (OPC) and/or trial and error. The initial reticle layout may, for instance, be generated completely through experience with particular reticle layouts, or by generating serifs using one of the many known OPC algorithms and modifying the serifs, e.g., shrinking them in size. The generation of the initial reticle layout is not limited by the present invention, which can be applied to any initial reticle layout.
A modified reticle layout is then generated which includes the reticle features of the initial reticle layout plus one or more sub-resolution connecting structures in accordance with the present invention. The sub-resolution connecting structures connect at least one set of two or more of the reticle features contained in the initial reticle layout. Because the sub-resolution connecting structures connect reticle features, the modified reticle layout will include fewer shapes than the number of features contained in the desired circuit feature layout. Likewise, individual shapes in the modified reticle layout which include, for example, two reticle features connected by a sub-resolution connecting structure will print as two separate features.
Prior to making a reticle corresponding to the modified reticle layout, the modified reticle layout is preferably checked to analyze differences between the pattern that will be produced on a resist and the desired circuit feature layout. Depending on the differences, additional modifications can be made to the modified reticle layout, which may include changes to one or more of the printable reticle features and/or addition or removal of one or more of the sub-resolution connecting structures.
The present invention also relates to reticles which include one or more sub-resolution connecting structures which connect two or more printable reticle features, each designed to print separate circuit features in the desired circuit feature layout.
The present invention is further directed to integrated circuits which incorporate one or more components made using any of the reticles according to the present invention, e.g., the reticles of the present invention can be used in making such components.
These and other features and advantages of the invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which is provided in conjunction with the accompanying drawings. The invention is not limited to the exemplary embodiments described below and it should recognized that the invention includes all modifications falling within the scope of the attached claims.